FPGA Verification Engineer (m/f)
ZG - Savska Opatovina, Croatia
Rimac Automobili is a technology powerhouse, manufacturing electric hypercars and providing full tech solutions to global automotive manufacturers. Our teams develop and produce both hardware and software solutions for the Concept_One and C_Two as well as numerous public and confidential projects, thus positioning Rimac as a leader in the high-performance electric vehicle industry.
We always wanted to be more than just a place to work. What we do and how all of our team members feel is meaningful to us and we want each to feel like part of a big family.
Rimac Automobili is a technology powerhouse, manufacturing electric hypercars and providing full tech solutions to global automotive manufacturers. Our teams develop and produce both hardware and software solutions for the Concept_One and C_Two as well as numerous public and confidential projects, thus positioning Rimac as a leader in the high-performance electric vehicle industry.
We always wanted to be more than just a place to work. What we do and how all of our team members feel is meaningful to us and we want each to feel like part of a big family.
We are now looking for FPGA Verification Engineers. We are open to receive applications from all candidates with any experience.
You will be developing an FPGA design. We typically assemble small, cross-functional project teams who take ownership of a specific system and develop it end-to-end. This is a fast-paced environment where you will have to think on your feet and perform well under pressure in order to deliver next-generation technology for the Automotive sector.
1. Responsibilities:
FPGA design verification
Designing UVM test benches and testing existing design
Create and enhance constrained-random verification environments using SystemVerilog and UVM
Develop Test Plan (coverage driven & constraint random verification)
Assistance in digital architecture design
Collaborating with our FPGA development engineering team and a multidisciplinary team of engineers
Close coverage measures to identify verification holes and to show progress towards tape-out.
2. Requirements:
Strong development skills in SystemVerilog
Familiarity with verification environments e.g. UVM
Knowledge of Object-Oriented programming
Knowledge of scripting languages
Should be a great teammate with excellent communication skills.
Experience with communication protocols (CAN, SPI, I2C, UART, etc)
Advanced knowledge of English (written and spoken)
Experience with troubleshooting/debugging tools as well as lab equipment
Experience with Xilinx, Mentor Graphics tools
3. What we offer
We thank all those who submit applications for this role. Please note that only those candidates who meet the required experience and qualifications will be contacted directly. All of our applicants will be provided with equal opportunities regardless of their age, sex, race, disability, sexual orientation, culture or any other non-work related personal characteristic. All applications will be considered under the terms and conditions of confidentiality in accordance with the regulations of personal data protection.